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4-channel, 625 ksps, 12-bit parallel adc with a sequencer ad7934-6 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005C2007 analog devices, inc. all rights reserved. features throughput rate: 625 ksps specified for v dd of 2.7 v to 5.25 v power consumption 3.6 mw maximum at 625 ksps with 3 v supplies 7.5 mw maximum at 625 ksps with 5 v supplies 4 analog input channels with a sequencer software-configurable analog inputs 4-channel single-ended inputs 2-channel fully differential inputs 2-channel pseudo differential inputs accurate on-chip 2.5 v reference 0.2% maximum @ 25c, 25 ppm/c maximum 70 db sinad at 50 khz input frequency no pipeline delays high speed parallel interfaceword/byte modes full shutdown mode: 2 a maximum 28-lead tssop package functional block diagram 04752-001 v in 3 t/h parallel interface/control register sequencer 12-bit sar adc and control i/p mux 2.5v vref db0 db11 v drive v dd ad7934-6 v in 0 agnd v refin / v refout clkin busy convst cs dgnd rd wr w/b figure. 1 general description the ad7934-6 is a 12-bit, high speed, low power, successive approximation (sar) analog-to-digital converter (adc). the part operates from a single 2.7 v to 5.25 v power supply and features throughput rates up to 625 ksps. the part contains a low noise, wide bandwidth, differential track-and-hold amplifier that handles input frequencies up to 50 mhz. the ad7934-6 features four analog input channels with a channel sequencer that allows a preprogrammed selection of channels to be converted sequentially. this part can accept either single- ended, fully differential, or pseudo differential analog inputs. data acquisition and conversion are controlled by standard control inputs that allow for easy interfacing to microprocessors and dsps. the input signal is sampled on the falling edge of convst , which is also the point where the conversion is initiated. the ad7934-6 has an accurate on-chip 2.5 v reference that can be used as the reference source for the analog-to-digital conversion. alternatively, this pin can be overdriven to provide an external reference. the ad7934-6 uses advanced design techniques to achieve very low power dissipation at high throughput rates. the part also features flexible power management options. an on-chip control register allows the user to set up different operating conditions, including analog input range and configuration, output coding, power management, and channel sequencing. product highlights 1. high throughput with low power consumption. 2. four analog inputs with a channel sequencer. 3. accurate on-chip 2.5 v reference. 4. single-ended, pseudo differential, or fully differential analog inputs that are software selectable. 5. no pipeline delay. 6. accurate control of the sampling instant via a convst input and once-off conversion control. table 1. related devices similar device no. of bits no. of channels speed ad7938 / ad7939 12/10 8 1.5 msps ad7933 / ad7934 10/12 4 1.5 msps ad7938-6 12 8 625 ksps
ad7934-6* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. documentation data sheet ? ad7934-6: 4-channel, 625 ksps, 12-bit parallel adc with a sequencer data sheet reference materials technical articles ? ms-2210: designing power supplies for high speed adc design resources ? ad7934-6 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad7934-6 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
ad7934-6 rev. b | page 2 of 28 table of contents features .............................................................................................. 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 7 typical performance characteristics ............................................. 9 terminology .................................................................................... 11 control register.............................................................................. 13 sequencer operation ................................................................. 14 circuit information ........................................................................ 15 converter operation.................................................................. 15 adc transfer function............................................................. 15 typical connection diagram ................................................... 16 analog input structure.............................................................. 16 analog input configurations ................................................... 17 analog input selection .............................................................. 19 reference ..................................................................................... 20 parallel interface......................................................................... 21 power modes of operation ....................................................... 24 power vs. throughput rate....................................................... 25 microprocessor interfacing....................................................... 25 application hints ........................................................................... 27 grounding and layout .............................................................. 27 evaluating the ad7934-6 performance .................................. 27 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history 2/07rev. a to rev. b updated format..................................................................universal changes to figure 13...................................................................... 10 changes to sequencer operation section................................... 14 changes to figure 34...................................................................... 21 10/05rev. 0 to rev. a changes to product highlights....................................................... 1 inserted table 1................................................................................. 1 changes to specifications ................................................................ 3 changes to timing specifications .................................................. 5 changes to pin function descriptions.......................................... 7 added writing to the control register to program the sequencer section.................................................... 14 changes to the analog inputs section......................................... 17 changes to the grounding and layout section ......................... 27 1/05revision 0: initial version
ad7934-6 rev. b | page 3 of 28 specifications v dd = v drive = 2.7 v to 5.25 v, internal/external v ref = 2.5 v, unless otherwise noted, f clkin = 10 mhz, f sample = 625 ksps; t a = t min to t max x 1 , unless otherwise noted. table 2. parameter value 1 unit test conditions/comments dynamic performance f in = 50 khz sine wave signal-to-noise + d istortion (sinad) 2 70 db min differential mode 68 db min single-ended mode signal-to-noise ratio (snr) 2 71 db min differential mode 69 db min single-ended mode total harmonic distortion (thd) 2 ?73 db max ?85 db typ, differential mode ?70 db max ?80 db typ, single-ended mode peak harmonic or spurious noise (sfdr) 2 ?73 db max ?82 db typ intermodulation distortion (imd) 2 fa = 30 khz, fb = 50 khz second-order terms ?86 db typ third-order terms ?90 db typ channel-to-channel isolation ?85 db typ f in = 50 khz, f noise = 300 khz aperture delay 2 5 ns typ aperture jitter 2 72 ps typ full power bandwidth 2 50 mhz typ @ 3 db 10 mhz typ @ 0.1 db dc accuracy resolution 12 bits integral nonlinearity 2 1 lsb max differential mode 1.5 lsb max single-ended mode differential nonlinearity 2 differential mode 0.95 lsb max guaranteed no missed codes to 12 bits single-ended mode ?0.95/+1.5 lsb max guaranteed no missed codes to 12 bits single-ended and pseudo differential input straight binary output coding offset error 2 6 lsb max offset error match 2 1 lsb max gain error 2 3 lsb max gain error match 2 1 lsb max fully differential input twos complement output coding positive gain error 2 3 lsb max positive gain error match 2 1 lsb max zero-code error 2 6 lsb max zero-code error match 2 1 lsb max negative gain error 2 3 lsb max negative gain error match 2 1 lsb max analog input single-ended input range 0 to v ref v range bit = 0 0 to 2 v ref v range bit = 1 pseudo differential input range v in+ 0 to v ref v range bit = 0 0 to 2 v ref v range bit = 1 v in? ?0.3 to +0.7 v typ v dd = 3 v ?0.3 to +1.8 v typ v dd = 5 v fully differential input range 3 v in+ and v in? v cm v ref /2 v v cm = v ref /2, range bit = 0 v in+ and v in? v cm v ref v v cm = v ref , range bit = 1 dc leakage current 4 1 a max input capacitance 45 pf typ when in track 10 pf typ when in hold
ad7934-6 rev. b | page 4 of 28 parameter value 1 unit test conditions/comments reference input/output v ref input voltage 5 2.5 v 1% for specified performance dc leakage current 4 1 a max v refout output voltage 2.5 v 0.2% max @ 25c v refout temperature coefficient 25 ppm/c max 5 ppm/c typ v ref noise 10 v typ 0.1 hz to 10 hz bandwidth 130 v typ 0.1 hz to 1 mhz bandwidth v ref output impedance 10 typ v ref input capacitance 15 pf typ when in track 25 pf typ when in hold logic inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i in 5 a max typically 10 na, v in = 0 v or v drive input capacitance, c in 4 10 pf max logic outputs output high voltage, v oh 2.4 v min i source = 200 a output low voltage, v ol 0.4 v max i sink = 200 a floating-state leakage current 3 a max floating-state ou tput capacitance 4 10 pf max output coding straight (natural) binary coding bit = 0 twos complement coding bit = 1 conversion rate conversion time t 2 + 13 t clkin ns track-and-hold acquisition time 125 ns max full-scale step input 80 ns typ sine wave input throughput rate 625 ksps max power requirements v dd 2.7/5.25 v min/max v drive 2.7/5.25 v min/max i dd 6 digital i/p s = 0 v or v drive normal mode (static) 0.8 ma typ v dd = 2.7 v to 5.25 v, sclk on or off normal mode (operational) 1.5 ma max v dd = 4.75 v to 5.25 v 1.2 ma max v dd = 2.7 v to 3.6 v autostandby mode 0.3 ma typ f sample = 100 ksps, v dd = 5 v 160 a typ static, v dd = 3 v full/autoshutdown mode (static) 2 a max sclk on or off power dissipation normal mode (operational) 7.5 mw max v dd = 5 v 3.6 mw max v dd = 3 v autostandby mode (static) 800 w typ v dd = 5 v 480 w typ v dd = 3 v full/autoshutdown mode 10 w max v dd = 5 v 6 w max v dd = 3 v 1 temperature range is as follows: b version: ?40c to +85c. 2 see the terminology section. 3 v cm is the common-mode voltage. for full common-mode range, see figure 25 and figure 26. v in+ and v in? must always remain within gnd/v dd . 4 sample tested during initial release to ensure compliance. 5 this device is operational with an extern al reference in the range of 0.1 v to v dd . see the reference sectio n for more in formation. 6 measured with a midscale dc analog input.
ad7934-6 rev. b | page 5 of 28 timing specifications v dd = v drive = 2.7 v to 5.25 v, internal/external v ref = 2.5 v, unless otherwise noted. f clkin = 10 mhz, f sample = 625 ksps, t a = t min to t max , unless otherwise noted. table 3. parameter 1 limit at t min , t max unit description f clkin 2 700 khz min clkin frequency 10 mhz max t quiet 30 ns min minimum time between end of read and start of next conversion, that is, time from when the data bus goes into three-state until the next falling edge of convst t 1 10 ns min convst pulse width t 2 15 ns min convst falling edge to clkin falling edge setup time t 3 50 ns max clkin falling edge to busy rising edge t 4 0 ns min cs to wr setup time t 5 0 ns min cs to wr hold time t 6 10 ns min wr pulse width t 7 10 ns min data setup time before wr t 8 10 ns min data hold after wr t 9 10 ns min new data valid before falling edge of busy t 10 0 ns min cs to rd setup time t 11 0 ns min cs to rd hold time t 12 30 ns min rd pulse width t 13 3 30 ns max data access time after rd t 14 4 3 ns min bus relinquish time after rd 50 ns max bus relinquish time after rd t 15 0 ns min hben to rd setup time t 16 0 ns min hben to rd hold time t 17 10 ns min minimum time between reads/writes t 18 0 ns min hben to wr setup time t 19 10 ns min hben to wr hold time t 20 40 ns max clkin falling edge to busy falling edge t 21 15.7 ns min clkin low pulse width t 22 7.8 ns min clkin high pulse width 1 sample tested during initial release to ensure compliance. all input signals are specified with t rise = t fall = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. all timing specifications given ab ove are with a 25 pf load capacitance. see figure 34, figure 35, figure 36, and figure 37. 2 minimum clkin for specified performance. with slower clkin frequencies, performance specifications apply typically. 3 the time required for the output to cross 0.4 v or 2.4 v. 4 t 14 is derived from the measured time taken by the data outputs to change 0.5 v. the measured number is then extrapolated back to remove the effects of charging or discharging the 25 pf capacitor. this means that the time, t 14 , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
ad7934-6 rev. b | page 6 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter rating v dd to agnd/dgnd ?0.3 v to +7 v v drive to agnd/dgnd ?0.3 v to v dd + 0.3 v analog input voltage to agnd ?0.3 v to v dd + 0.3 v digital input voltage to dgnd ?0.3 v to +7 v v drive to v dd ?0.3 v to v dd + 0.3 v digital output voltage to dgnd ?0.3 v to v drive + 0.3 v v refin to agnd ?0.3 v to v dd + 0.3 v agnd to dgnd ?0.3 v to +0.3 v input current to any pin except supplies 1 10 ma operating temperature range commercial (b version) ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance 97.9c/w (tssop) jc thermal impedance 14c/w (tssop) lead temperature, soldering reflow temperature (10 sec to 30 sec) 255c esd 1.5 kv 1 transient currents of up to 100 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7934-6 rev. b | page 7 of 28 pin configuration and fu nction descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 w/b db0 db1 db4 db3 db2 v dd v in 2 v in 1 v in 0 cs agnd v refin /v refou t db5 db6 db7 db9 dgnd v drive rd wr convst db10 db8/hben db11 busy clkin v in 3 ad7934-6 top view (not to scale) 04752-006 figure 2. table 5. pin function descriptions pin no. mnemonic description 1 v dd power supply input. the v dd range for the ad7934-6 is from 2.7 v to 5.25 v. the supply should be decoupled to agnd with a 0.1 f capacitor and a 10 f tantalum capacitor. 2 w/ b word/byte input. when this input is logic high, word tran sfer mode is enabled, and data is transferred to and from the ad7934-6 in 12-bit words on pin db0 to pin db11. when w/ b is logic low, byte transfer mode is enabled. data and the channel id are transferred on pi n db0 to pin db7, and pin db8/hben assumes its hben functionality. when operating in byte transfer mode, unused data lines should be tied off to dgnd. 3 to 10 db0 to db7 data bit 0 to data bit 7. three-state parallel digital i/ o pins that provide the conversion result, and allow the control register to be programmed. these pins are controlled by cs , rd , and wr . the logic high/low voltage levels for these pins are determined by the v drive input. 11 v drive logic power supply input. the voltage supplied at this pin determines what voltage the parallel interface of the ad7934-6 operates. this pin should be decoupled to dgn d. the voltage at this pin can be different to that at v dd , but should never exceed v dd by more than 0.3 v. 12 dgnd digital ground. this is the ground reference point for all digital circuitry on the ad7934-6. this pin should connect to the dgnd plane of a system. the dgnd and agnd voltages should ideally be at the same potential, and must not be more than 0.3 v apart, even on a transient basis. 13 db8/hben data bit 8/high byte enable. when w/ b is high, this pin acts as data bi t 8, a three-state i/o pin that is controlled by cs , rd , and wr . when w/ b is low, this pin acts as the high byte enable pin. when hben is low, the low byte of data written to or read from the ad7934- 6 is on db0 to db7. when hben is high, the top four bits of the data being written to or read from the ad 7934-6 are on db0 to db3. when reading from the device, db4 and db5 of the high byte contain the id of the ch annel corresponding to the conversion result (see the channel address bits in table 9 ). db6 and db7 are always 0. when writing to the device, db4 to db7 of the high byte must all be 0s. 14 to 16 db9 to db11 data bit 9 to data bit 11. three-state parallel digital i/o pins that provide the conversion result and allow the control register to be programmed in word mode. these pins are controlled by cs , rd , and wr . the logic high/low voltage levels for these pins are determined by the v drive input. 17 busy busy output. logic output indicating the status of th e conversion. the busy output goes high following the falling edge of convst and stays high for the duration of the co nversion. once the conversion is complete and the result is available in the output register, the bu sy output goes low. the track-and-hold returns to track mode just prior to the falling edge of busy, on the 13 th rising edge of clkin (see figure 34 ). 18 clkin master clock input. the clock source for the conversion pr ocess is applied to this pi n. conversion time for the ad7934-6 takes 13 clock cycles + t 2 . the frequency of the master clock input therefore determines the conversion time and achievable throughput rate. the cl kin signal can be a continuous or burst clock. 19 convst conversion start input. a falling edge on convst is used to initiate a conversion. the track-and-hold goes from track to hold mode on the falling edge of convst , and the conversion process is initiated at this point. following power-down, when operating in the autosh utdown or autostandby mode, a rising edge on convst is used to power up the device. 20 wr write input. active low logic input used in conjunction with cs to write data to the control register. 21 rd read input. active low logic input used in conjunction with cs to access the conversion result. the conversion result is placed on the data bus following the falling edge of rd read while cs is low.
ad7934-6 rev. b | page 8 of 28 pin no. mnemonic description 22 cs chip select. active low logic input used in conjunction with rd and wr to read conversion data or write data to the control register. 23 agnd analog ground. this is the ground reference point for all analog circuitry on the ad7934-6. all analog input signals and any external reference signal should be referred to this agnd voltage. the agnd and dgnd voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 24 v refin /v refout reference input/output. this pin is connected to the in ternal reference, and is the reference source for the adc. the nominal internal reference voltage is 2.5 v, and it appears at this pin. it is recommended that this pin be decoupled to agnd with a 470 nf capacitor. this pin can be overdriven by an external reference. the input voltage range for the external reference is 0.1 v to v dd ; however, care must be taken to ensure that the analog input range does not exceed v dd + 0.3 v. see the reference section. 25 to 28 v in 0 to v in 3 analog input 0 to analog input 3. fo ur analog input channels that are mu ltiplexed into the on-chip track-and- hold. the analog inputs can be programmed to be four si ngle-ended inputs, two fully differential pairs, or two pseudo differential pairs by setting the mode bits in the control register appropriately (see table 9 ). the analog input channel to be converted can be selected either by writing to the address bits (add1 and add0) in the control register prior to the conversion, or by using the on-chip sequencer. the input range for all input channels can be either 0 v to v ref , or 0 v to 2 v ref , and the coding can be binary or twos complement, depending on the states of the range and coding bits in the control register. any unused input channels should be connected to agnd to avoid noise pickup.
ad7934-6 rev. b | page 9 of 28 typical performance characteristics t a = 25c, unless otherwise noted. supply ripple frequency (khz) psrr (db) ? 60 ?70 ?80 ?90 ?110 ?100 ?120 10 210 610 410 810 1010 04752-007 100mv p-p sine wave on v dd and/or v drive no decoupling differential/single-ended mode int ref ext ref figure 3. psrr vs. supply ripple freq uency without supply decoupling noise frequency (khz) noise isolation (db) ? 70 ?75 ?90 ?85 ?80 ?95 0 100 400 200 300 600 500 800 700 04752-021 internal/external reference v dd =5v figure 4. channel- to-channel isolation frequency (khz) sinad (db) 80 70 60 50 30 40 20 0 100 400 200 300 600500 1000 700 800 900 04752-008 f sample = 625ksps range = 0 to v ref differential mode v dd =5v v dd =3v figure 5. sinad vs. analog input frequency for various supply voltages frequency (khz) ??? 0 ?10 ?20 ?50 ?40 ?30 ?90 ?100 ?80 ?70 ?60 ?110 0 100 200 300 400 500 600 700 04752-009 4096 point fft v dd =5v f sample = 625ksps f in = 49.62khz sinad = 70.94db thd = ?90.09db differential mode amplitude (db) figure 6. fft @ v dd = 5 v code dnl error (lsb) 1.0 0.8 0.6 0.4 0.2 ?0.2 0 ?0.8 ?0.6 ?0.4 ?1.0 0 500 2000 1000 1500 3000 2500 4000 3500 04752-010 v dd = 5v differential mode figure 7. typical dnl @ v dd = 5 v code inl error (lsb) 1.0 0.8 0.6 0.4 0.2 ?0.2 0 ?0.8 ?0.6 ?0.4 ?1.0 0 500 2000 1000 1500 3000 2500 4000 3500 04752-011 v dd =5v differential mode figure 8. typical inl @ v dd = 5 v
ad7934-6 rev. b | page 10 of 28 v ref (v) dnl (lsb) 4 3 1 2 0 ?1 0.25 0.50 1.25 0.75 1.00 2.001.751.50 2.75 2.50 2.25 04752-012 single-ended mode positive dnl negative dnl figure 9. dnl vs. v ref for v dd = 3 v v ref (v) effective number of bits 12 11 10 8 9 7 6 00.5 1.5 1.0 2.5 2.0 4.0 3.5 3.0 04752-013 v dd =5v differential mode v dd =5v single-ended mode v dd =3v single-ended mode v dd =3v differential mode figure 10. enob vs. v ref v ref (v) offset (lsb) 0 ?0.5 ?1.5 ?1.0 ?3.5 ?3.0 ?2.5 ?2.0 ?4.0 ?4.5 ?5.0 00.5 1.5 1.0 2.5 2.0 3.5 3.0 04752-014 single-ended mode v dd =5v v dd =3v figure 11. offset vs. v ref code ??? 10000 9000 7000 8000 3000 4000 5000 6000 2000 1000 0 2046 2047 2048 2049 2050 04752-015 differential mode 3codes internal ref 9997 codes figure 12. histogram of codes for 10,000 samples @ v dd = 5 v with internal reference ripple frequency (khz) cmrr (db) 60 70 80 100 90 110 120 0 200 400 800 600 1200 1000 04752-017 differential mode figure 13. cmrr vs. ripple frequency with v dd = 5 v and 3 v
ad7934-6 rev. b | page 11 of 28 terminology integral nonlinearity (inl) this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, 1 lsb below the first code transition, and full scale, 1 lsb above the last code transition. differential nonlinearity (dnl) this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (00000) to (00001) from the ideal (that is, agnd + 1 lsb). offset error match this is the difference in offset error between any two channels. gain error this is the deviation of the last code transition (111110) to (111111) from the ideal (that is, v ref C 1 lsb) after the offset error has been adjusted out. gain error match this is the difference in gain error between any two channels. zero-code error this applies when using the twos complement output coding option, in particular to the 2 v ref input range, with ?v ref to +v ref biased about the v ref point. it is the deviation of the midscale transition (all 0s to all 1s) from the ideal v in voltage (that is, v ref ). zero-code error match this is the difference in zero-code error between any two channels. positive gain error this applies when using the twos complement output coding option, in particular to the 2 v ref input range, with ?v ref to +v ref biased about the v ref point. it is the deviation of the last code transition (011110) to (011111) from the ideal (that is, +v ref C 1 lsb) after the zero-code error has been adjusted out. positive gain error match this is the difference in positive gain error between any two channels. negative gain error this applies when using the twos complement output coding option, in particular to the 2 v ref input range, with ?v ref to +v ref biased about the v ref point. it is the deviation of the first code transition (100 000) to (100 001) from the ideal (that is, ?v ref + 1 lsb) after the zero-code error has been adjusted out. negative gain error match this is the difference in negative gain error between any two channels. channel-to-channel isolation this is a measure of the level of crosstalk between channels. it is measured by applying a full-scale sine wave signal to the three, nonselected input channels and applying a 50 khz signal to the selected channel. the channel-to-channel isolation is defined as the ratio of the power of the 50 khz signal on the selected channel to the power of the noise signal on the unse- lected channels that appears in the fast fourier transform (fft) of this channel. the noise frequency on the unselected channels varies from 40 khz to 740 khz. the noise amplitude is at 2 v ref , while the signal amplitude is at 1 v ref . see figure 4 . power supply rejection ratio (psrr) psrr is defined as the ratio of the power in the adc output at full-scale frequency (f) to the power of a 100 mv p-p sine wave applied to the adc v dd supply of frequency f s . the frequency of the noise varies from 1 khz to 1 mhz. psrr (db) = 10 log( pf / pf s ) where: pf is the power at frequency f in the adc output. pf s is the power at frequency f s in the adc output. common-mode rejection ratio (cmrr) cmrr is defined as the ratio of the power in the adc output at full-scale frequency, f, to the power of a 100 mv p-p sine wave applied to the common-mode voltage of v in+ and v in? of frequency, f s . cmrr (db) = 10 log( pf/pf s ) where: pf is the power at frequency f in the adc output. pf s is the power at frequency f s in the adc output.
ad7934-6 rev. b | page 12 of 28 track-and-hold acquisition time the track-and-hold amplifier returns to track mode at the end of conversion. the track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ? lsb, after the end of conversion. signal-to-noise and distortion ratio (sinad) this is the measured ratio of signal-to-noise and distortion at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f sample /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical sinad ratio for an ideal n-bit converter with a sine wave input is given by: sinad = (6.02 n + 1.76) db thus, for a 12-bit converter, sinad is 74 db. total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the fundamental. for the ad7934-6, it is defined as: () ? ? ? ? ? ? ? ? ++++ ?= 1 6 54 32 v vvvvv thd 22222 log20db where: v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise this is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f sample /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second-order terms include (fa + fb) and (fa ? fb), while the third-order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the ad7934-6 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second-order terms are usually distanced in frequency from the original sine waves, while the third-order terms are usually at a frequency close to the input frequencies. as a result, the second- and third-order terms are specified separately. the intermodulation distortion is calculated per the thd specification, as the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in db.
ad7934-6 rev. b | page 13 of 28 control register the control register on the ad7934-6 is a 12-bit, write-only register. data is written to this register using the cs and wr pins. the control register is shown in table 6 and the functions of the bits are described in table 7 . at power-up, the default bit settings in the control register are all 0s. table 6. control register bits msb lsb db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 pm1 pm0 coding ref zero add1 add0 mode1 mode0 seq1 seq0 range table 7. control register bit function description bit no. mnemonic description 11, 10 pm1, pm0 power management bits used to select the power mode of operation. the user can choose between normal mode and various power-down modes of operation, as shown in table 8 . 9 coding selects the output coding of the conversion result. if set to 0, the output coding is straight (natural) binary. if set to 1, the output coding is twos complement. 8 ref selects whether the internal or external reference is used to perform the conversion. if this bit is logic 0, an external reference should be applied to the v ref pin. if this bit is logic 1, the internal reference is selected. see the reference section. 7 zero not used. this bit should always be set to logic 0. 6, 5 add1, add0 two address bits that either select which analog input ch annel is to be converted in the next conversion, if the sequencer is not used, or select the final channel in a consecutive sequence when the sequencer is used, as described in table 10 . the selected input channel is decoded as shown in table 9 . 4, 3 mode1, mode0 two mode pins that select the type of analog input on the four v in pins. the ad7934-6 has four single-ended inputs, two fully differential inputs, or two pseudo differential inputs. see table 9 . 2 seq1 used in conjunction with the seq0 bit to control the sequencer function. see table 10 . 1 seq0 used in conjunction with the seq1 bit to control the sequencer function. see table 10 . 0 range selects the analog input range of the ad7934-6. if set to 0, the analog input range extends from 0 v to v ref . if it is set to 1, the analog input range extends from 0 v to 2 v ref . when this range is selected, v dd must be 4.75 v to 5.25 v if a 2.5 v reference is used; otherwise, care must be taken to ensure that the analog input remains within the supply rails. see the analog input configurations section for more information. table 8. power mode selection using the power management bits in the control register pm1 pm0 mode description 0 0 normal mode when operating in normal mode, all circuitry is fully powered up at all times. 0 1 autoshutdown when operating in autoshutdown mode, the ad7934-6 enters full shutdown mode at the end of each conversion. in this mode, all circuitry is powered down. 1 0 autostandby when the ad7934-6 enters this mode, the reference remain s fully powered, the reference buffer is partially powered down, and all other circuitry is fully powered down. this mode is simila r to autoshutdown mode, but it allows the part to power up in 7 s (or 600 ns if an external reference is used). see the power modes of operation section for more information. 1 1 full shutdown when the ad7934-6 enters this mode, all circuitry is po wered down. the information in the control register is retained. table 9. analog input type selection mode0 = 0, mode1 = 0 mode0 = 0, mode1 = 1 mode0 = 1, mode1 = 0 mode0 = 1, mode1 = 1 channel address four single-ended input channels two fully differential input channels two pseudo differential input channels not used add1 add0 v in+ v in? v in+ v in? v in+ v in? 0 0 v in 0 agnd v in 0 v in 1 v in 0 v in 1 0 1 v in 1 agnd v in 1 v in 0 v in 1 v in 0 1 0 v in 2 agnd v in 2 v in 3 v in 2 v in 3 1 1 v in 3 agnd v in 3 v in 2 v in 3 v in 2
ad7934-6 rev. b | page 14 of 28 sequencer operation the configuration of the seq0 and seq1 bits in the control register allows the user to use the sequencer function. table 10 outlines the two sequencer modes of operation. writing to the control register to program the sequencer the ad7934-6 needs 13 full clkin periods to perform a conversion. if the adc does not receive the full 13 clkin periods, the conversion aborts. if a conversion is aborted after applying 12.5 clkin periods to the adc, ensure that a rising edge of convst or a falling edge of clkin is applied to the part before writing to the control register to program the sequencer. if these conditions are not met, the sequencer will not be in the correct state to handle being reprogrammed for another sequence of conversions and the performance of the converter is not guaranteed. table 10. sequence selection modes seq0 seq1 sequence type 0 0 this configuration is selected when the sequence function is not used. the analog input channel selected on each individual conversion is determined by the contents of th e channel address bits, add1 and add0, in each prior write operation. this mode of operation reflects the normal operati on of a multichannel adc, without the sequencer function being used, where each write to the ad7934-6 selects the next channel for conversion. 0 1 not used. 1 0 not used. 1 1 this configuration is used in conjunction with the chan nel address bits, add1 and add0, to program continuous conversions on a consecutive sequence of channels from channel 0 to a selected final channel, as determined by the channel address bits in the control register. when in differ ential or pseudo differential mode, inverse channels (for example, v in 1, v in 0) are not converted in this mode.
ad7934-6 rev. b | page 15 of 28 circuit information the ad7934-6 is a fast, 4-channel, 12-bit, single-supply, successive approximation analog-to-digital converter. the part operates from a 2.7 v to 5.25 v power supply and features throughput rates up to 625 ksps. the ad7934-6 provides the user with an on-chip track-and- hold, an accurate internal reference, an analog-to-digital converter, and a parallel interface housed in a 28-lead tssop package. the ad7934-6 has four analog input channels that can be configured to be four single-ended inputs, two fully differential pairs or two pseudo differential pairs. an on-chip channel sequencer allows the user to select a consecutive sequence of channels through which the adc can cycle with each falling edge of convst . the analog input range for the ad7934-6 is 0 v to v ref , or 0 v to 2 v ref , depending on the status of the range bit in the control register. the output coding of the adc can be either straight binary or twos complement, depending on the status of the coding bit in the control register. the ad7934-6 provides flexible power management options to allow users to achieve the best power performance for a given throughput rate. these options are selected by programming the power management bits, pm1 and pm0, in the control register. converter operation the ad7934-6 is a successive approximation adc based on two capacitive digital-to-analog converters (dacs). figure 14 and figure 15 show simplified schematics of the adc in acquisition and conversion phase, respectively. the adc comprises control logic, sar, and two capacitive dacs. both figures show the operation of the adc in differential/pseudo differential mode. single-ended mode operation is similar but v in? is internally tied to agnd. in the acquisition phase, sw3 is closed, sw1 and sw2 are in position a, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. 04752-023 v in+ v in? a b sw1 sw3 comparator control logic capacitive dac capacitive dac c s c s v ref sw2 b a figure 14. adc acquisition phase when the adc starts a conversion (see figure 15 ), sw3 opens, and sw1 and sw2 move to position b, causing the comparator to become unbalanced. both inputs are disconnected once the conversion begins. the control logic and charge redistribution dacs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the output code of the adc. the output impedances of the sources driving the v in+ and the v in? pins must match; otherwise, the two inputs have different settling times, resulting in errors. 04752-024 v in+ v in? a b sw1 sw3 comparator control logic capacitive dac capacitive dac c s c s v ref sw2 b a figure 15. adc conversion phase adc transfer function the output coding for the ad7934-6 is either straight binary or twos complement, depending on the status of the coding bit in the control register. the designed code transitions occur at successive lsb values (that is, 1 lsb, 2 lsbs, and so on), and the lsb size is v ref /4096. the ideal transfer characteristics of the ad7934-6 for both straight binary and twos complement output coding are shown in figure 16 and figure 17 , respectively. 04752-025 000...000 111...111 1lsb=v ref /4096 1lsb +v ref ?1lsb analog input adc code 0v notes 1. v ref is either v ref or 2 v ref . 000...001 000...010 111...110 111...000 011...111 figure 16. ideal transfer characteristic with straight bina ry output coding
ad7934-6 rev. b | page 16 of 28 0 4752-026 100...000 011...111 1lsb=2v ref /4096 ?v ref +1lsb v ref +v ref ?1lsb adc code 100...001 100...010 011...110 000...001 000...000 111...111 figure 17. ideal transfer characteristic with twos complement output coding and 2 x v ref range typical connection diagram figure 18 shows a typical connection diagram for the ad7934-6. the agnd and dgnd pins are connected together at the device for good noise suppression. the v refin /v refout pin is decoupled to agnd with a 0.47 f capacitor to avoid noise pickup if the internal reference is used. alternatively, v refin /v refout can be connected to an external reference source. in this case, the reference pin should be decoupled with a 0.1 f capacitor. in both cases, the analog input range can either be 0 v to v ref (range bit = 0) or 0 v to 2 v ref (range bit = 1). the analog input configu- ration is either four single-ended inputs, two differential pairs or two pseudo differential pairs (see table 9 ). the v dd pin connects to either a 3 v or 5 v supply. the voltage applied to the v drive input controls the voltage of the digital interface. in figure 18 , it is connected to the same 3 v supply of the microprocessor to allow a 3 v logic interface (see the digital inputs section). 0.1f 10f 3v/5 v supply 3v supply ad7934-6 0.1f 0.1f external v ref 0.47f internal v ref 0 to v ref / 0 to 2 v ref agnd dgnd w/b clkin cs v drive v in 0 v dd v refin /v refout v in 3 10f 2.5v v ref rd convst wr busy db0 db11/db9 04752-027 + + + + + microcontroller/ microprocessor figure 18. typical connection diagram analog input structure figure 19 shows the equivalent circuit of the analog input structure of the ad7934-6 in differential/pseudo differential mode. in single-ended mode, v in? is internally tied to agnd. the four diodes provide esd protection for the analog inputs. care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mv. this causes the diodes to become forward-biased and start conducting into the substrate. these diodes can conduct up to 10 ma without causing irreversible damage to the part. the c1 capacitors in figure 19 are typically 4 pf, and can primarily be attributed to pin capacitance. the resistors are lumped components made up of the on resistance of the switches. the value of these resistors is typically about 100 . the c2 capacitors are the sampling capacitors of the adc and typically have a capacitance of 45 pf. r1 c2 v in+ v dd c1 d d 04752-028 r1 c2 v in? v dd c1 d d figure 19. equivalent analog input circuit, conversion phaseswitches open , track phaseswitches closed for ac applications, removing high frequency components from the analog input signal is recommended by the use of an rc low- pass filter on the relevant analog input pins. in applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances significantly affect the ac performance of the adc. this can necessitate the use of an input buffer amplifier. the choice of the op amp is a function of the particular application. when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance depends on the amount of thd that can be tolerated. the thd increases as the source impedance increases and performance degrades. figure 20 and figure 21 show a graph of the thd vs. source impedance with a 50 khz input tone for both v dd = 5 v and 3 v, in single-ended mode and fully differential mode, respectively.
ad7934-6 rev. b | page 17 of 28 r source ( ? ) thd (db) ? 40 ?45 ?50 ?55 ?80 ?75 ?70 ?65 ?60 ?90 ?85 10 100 1k 04752-018 f in = 50khz v dd =5v v dd =3v figure 20. thd vs. source impedance in single-ended mode r source ( ? ) thd (db) ? 60 ?80 ?75 ?70 ?65 ?100 ?85 ?90 ?95 10 100 1k 04752-019 f in = 50khz v dd =5v v dd =3v figure 21. thd vs. source impedance in fully differential mode figure 22 shows a graph of the thd vs. the analog input frequency for various supplies, while sampling at 625 khz with an sclk of 10 mhz. in this case, the source impedance is 10 . input frequency (khz) thd (db) ? 50 ?60 ?70 ?80 ?110 ?100 ?90 ?120 0 100 400 200 300 600 500 700 04752-020 f sample = 625ksps range = 0 to v ref v dd =3v single-ended mode v dd =5v/3v differential mode v dd =5v single-ended mode figure 22. thd vs. analog input frequency for various supply voltages analog input configurations the ad7934-6 has software-selectable analog input configura- tions. the user can choose either four single-ended inputs, two fully differential pairs, or two pseudo differential pairs. the analog input configuration is chosen by setting the mode0/mode1 bits in the internal control register (see table 9 ). single-ended mode the ad7934-6 can have four single-ended analog input channels by setting the mode0 and mode1 bits in the control register to 0. in applications where the signal source has a high impedance, it is recommended to buffer the analog input before applying it to the adc. an op amp suitable for this function is the ad8021. the analog input range of the ad7934-6 can be programmed to be either 0 v to v ref , or 0 v to 2 v ref . if the analog input signal to be sampled is bipolar, the internal reference of the adc can be used to externally bias up this signal to make it the correct format for the adc. figure 23 shows a typical connection diagram when operating the adc in single-ended mode. this diagram shows a bipolar signal of amplitude 1.25 v being preconditioned before it is applied to the ad7934-6. in cases where the analog input amplitude is 2.5 v, the 3r resistor can be replaced with a resistor of value r. the resultant voltage on the analog input of the ad7934-6 is a signal ranging from 0 v to 5 v. in this case, the 2 v ref mode can be used. 0.47f +1.25v v in r r r 3r 0v ? 1.25v +2.5 v 0v v in 0 v in 3 v refout ad7934-6* *additional pins omitted for clarity. 04752-031 figure 23. single-ended mode connection diagram differential mode the ad7934-6 can have two differential analog input pairs by setting the mode0 and mode1 bits in the control register to 0 and 1, respectively. differential signals have some benefits over single-ended signals, including noise immunity based on the devices common-mode rejection, and improvements in distortion performance. figure 24 defines the fully differential analog input of the ad7934-6.
ad7934-6 rev. b | page 18 of 28 04752-032 v ref p-p v in+ v in? v ref p-p *additional pins omitted for clarity. ad7934-6* common-mode voltage figure 24. differential input definition the amplitude of the differential signal is the difference between the signals applied to the v in+ and v in? pins in each differential pair (that is, v in+ ? v in? ). v in+ and v in? should be simultaneously driven by two signals, each of amplitude v ref (or 2 v ref depending on the range chosen), which are 180 out of phase. the amplitude of the differential signal is therefore ?v ref to +v ref peak-to-peak (that is, 2 v ref ), regardless of the common mode (cm). the common mode is the average of the two signals, (v in+ + v in? )/2, and is therefore the voltage on which the two inputs are centered. this results in the span of each input being cm v ref /2. this voltage must be set up externally, and its range varies with the reference value v ref . as the value of v ref increases, the common-mode range decreases. when driving the inputs with an amplifier, the actual common-mode range is determined by the amplifier output voltage swing. figure 25 and figure 26 show how the common-mode range typically varies with v ref for a 5 v power supply using the 0 v to v ref range or 0 v to 2 v ref range, respectively. the common mode must be in this range to guarantee the functionality of the ad7934-6. when a conversion takes place, the common mode is rejected. this results in a virtually noise-free signal of amplitude ?v ref to +v ref , corresponding to the digital codes 0 to 4096. if the 0 v to 2 v ref range is used, the input signal amplitude extends from ?2 v ref to +2 v ref . v ref (v) common-mode range (v) 3.5 3.0 2.0 1.5 2.5 1.0 0.5 0 00.5 1.5 1.0 2.0 2.5 3.0 04752-033 t a =25c figure 25. input common-mode range vs. v ref (0 v to v ref range, v dd = 5 v) v ref (v) common-mode range (v) 4.5 4.0 3.0 1.5 2.0 2.5 3.5 1.0 0.5 0 0.1 0.6 1.6 1.1 2.1 2.6 04752-034 t a =25c figure 26. input common-mode range vs. v ref (2 v ref range, v dd = 5 v) driving differential inputs differential operation requires that v in+ and v in? be simultane- ously driven with two equal signals that are 180 out of phase. the common mode must be set up externally and has a range that is determined by v ref , the power supply, and the particular amplifier used to drive the analog inputs. differential modes of operation with either an ac or a dc input provide the best thd performance over a wide frequency range. not all applications have a signal preconditioned for differential operation, so there is often a need to perform single-ended-to-differential conversion. using an op amp pair an op amp pair can be used to directly couple a differential signal to one of the analog input pairs of the ad7934-6. the circuit configurations in figure 27 and figure 28 show how a dual op amp can be used to convert a single-ended signal into a differential signal for both a bipolar and unipolar input signal, respectively. the voltage applied to point a sets up the common-mode voltage. in both diagrams, it is connected in some way to the reference, but any value in the common-mode range can be input to set up the common mode. a suitable dual op amp for use in this configuration to provide differential drive to the ad7934-6 is the ad8022 . it is advisable to take care when choosing the op amp; the selection depends on the required power supply and system performance objectives. the driver circuits in figure 27 and figure 28 are optimized for dc coupling applications requiring best distortion performance. the circuit configuration in figure 27 converts and level shifts a single-ended, ground- referenced, bipolar signal to a differential signal centered at the v ref level of the adc. the circuit configuration shown in figure 28 converts a unipolar, single-ended signal into a differential signal.
ad7934-6 rev. b | page 19 of 28 220? 10k? 2v ref p-p gnd 440 ? 220? 220? 20k ? 220? 27 ? 27 ? v+ v? v+ v? a v in+ v in? v ref ad7934-6 0.47f 04752-035 3.75v 2.5v 1.25v 3.75v 2.5v 1.25v + figure 27. dual op amp circuit to convert a single-ended bipolar signal into a differential unipolar signal 10k? v ref p-p v ref gnd 440? 220 ? 220 ? 220 ? 27? 27? v+ v? v+ v? a v in+ v in? v ref ad7934-6 0.47f 04752-036 3.75v 2.5v 1.25v 3.75v 2.5v 1.25v figure 28. dual op amp circuit to convert a single-ended unipolar signal into a differential signal another method of driving the ad7934-6 is to use the ad8138 differential amplifier. the ad8138 can be used as a single- ended-to-differential amplifier or as a differential-to-differential amplifier. the device is as easy to use as an op amp and greatly simplifies differential signal amplification and driving. pseudo differential mode the ad7934-6 can have two pseudo differential pairs by setting the mode0 and mode1 bits in the control register to 1 and 0, respectively. v in + is connected to the signal source, which must have an amplitude of v ref (or 2 v ref depending on the range chosen) to make use of the full dynamic range of the part. a dc input is applied to the v in? pin. the voltage applied to this input provides an offset from ground or a pseudo ground for the v in + input. the benefit of pseudo differential inputs is that they separate the analog input signal ground from the adc ground, allowing dc common-mode voltages to be cancelled. typically, the voltage range for the v in? pin while in pseudo differential mode can extend from ?0.3 v to +0.7 v when v dd = 3 v, or from ?0.3 v to +1.8 v when v dd = 5 v. figure 29 shows a connection diagram for the pseudo differential mode. v in+ v in? v ref ad7934-6* * additional pins omitted for clarity. 04752-037 v ref p-p 0.47f dc input voltage + figure 29. pseudo different ial mode connection diagram analog input selection as shown in table 9 , users can set up their analog input con- figuration by setting the values in the mode0 and mode1 bits in the control register. assuming the configuration has been chosen, there are two different ways of selecting the analog input to be converted, depending on the state of the seq0 and seq1 bits in the control register. traditional multichannel operation (seq0 = seq1 = 0) any one of four analog input channels or two pairs of channels can be selected for conversion in any order by setting the seq0 and seq1 bits in the control register to 0. the channel to be converted is selected by writing to the address bits, add1 and add0, in the control register to program the multiplexer prior to the conversion. this mode of operation is that of a traditional multichannel adc, where each data write selects the next channel for conversion. figure 30 shows a flowchart of this mode of operation. the channel configurations are shown in table 9 . power on write to the control register to set up operating mode, analog input, and output configuration. set seq0 = seq1 = 0. select the desired channel to convert on (add1 to add0). issue convst pulse to initiate a conversion on the selected channel. initiate a read cycle to read the data from the selected channel. initiate a write cycle to select the next channel to be converted on by changing the values of bits add2 to add0 in the control register. set seq0 = seq1 = 0. 04752-038 figure 30. traditional multichannel operation flow chart using the sequencer: consecutive sequence (seq0 = seq1 = 1) a sequence of consecutive channels can be converted beginning with channel 0, and ending with a final channel selected by writing to the add1 and add0 bits in the control register. this is done by setting the seq0 and seq1 bits in the control register to 1. in this mode, once the control register is written to, the next conversion is on channel 0, then channel 1, and so on, until the channel selected by the address bits (add1 and add0) is reached.
ad7934-6 rev. b | page 20 of 28 the adc then returns to channel 0 and starts the sequence again. the wr input must be kept high to ensure that the control register is not accidentally overwritten and the sequence inter- rupted. this pattern continues until the ad7934-6 is written to. figure 31 shows the flowchart of the consecutive sequence mode. power on write to the control register to set up operating mode, analog input, and output configuration. select final channel (add1 and add0) in consecutive sequence. set seq0 = seq1 = 1. continuously convert on a consecutive sequence of channels from channel 0 up to and including the previously selected final channel on add1 and add0 with each convst pulse. 04752-039 figure 31. consecutive sequence mode flow chart reference the ad7934-6 can operate with either the on-chip reference or external reference. the internal reference is selected by setting the ref bit in the internal control register to 1. a block diagram of the internal reference circuitry is shown in figure 32 . the internal reference circuitry includes an on-chip 2.5 v band gap reference and a reference buffer. when using the internal refer- ence, the v refin /v refout pin should be decoupled to agnd with a 0.47 f capacitor. this internal reference not only provides the reference for the analog-to-digital conversion, but it can also be used externally in the syst em. it is recommended that the reference output is buffered using an external precision op amp before applying it anywhere in the system. reference ad7934-6 adc buffer 04752-040 v refin / v refout figure 32. internal reference circuit block diagram alternatively, an external reference can be applied to the v refin /v refout pin of the ad7934-6. an external reference input is selected by setting the ref bit in the internal control register to 0. the external reference input range is 0.1 v to v dd . it is important to ensure that when choosing the reference value, the maximum analog input range (v in max ) is never greater than v dd + 0.3 v, in order to comply with the maximum ratings of the device. for example, if operating in differential mode and the reference is sourced from v dd , the 0 v to 2 v ref range cannot be used. this is because the analog input signal range now extends to 2 v dd , which exceeds maximum rating conditions. in the pseudo differential modes, the user must ensure that (v ref + v in? ) v dd when using the 0 v to v ref range, or that (2 v ref + v in? ) v dd when using the 2 v ref range. in all cases, the specified reference is 2.5 v. the performance of the part with different reference values is shown in figure 9 , figure 10 , and figure 11 . the value of the reference sets the analog input span and the common-mode voltage range. errors in the reference source result in gain errors in the ad7934-6 transfer function and add to the specified full-scale errors on the part. table 11 lists suitable voltage references available from analog devices that can be used. figure 33 shows a typical connection diagram for an external reference. table 11. examples of suit able voltage references reference output voltage (v) initial accuracy (% maximum) operating current (a) ad780 2.5/3 0.04 1000 adr421 2.5 0.04 500 adr420 2.048 0.05 500 04752-041 1 ad780 nc 8 2 +v in nc 7 3 gnd 6 4 temp 5 o/p select trim v out v ref 2.5v nc nc v dd nc = no connect 10nf 0.1f 0.1f 0.1f *additional pins omitted for clarity. ad7934-6* figure 33. typical v ref connection diagram digital inputs the digital inputs applied to the ad7934-6 are not limited by the maximum ratings that limit the analog inputs. instead, the digital inputs applied can go to 7 v. they are not restricted by the v dd + 0.3 v limit that is on the analog inputs. another advantage of the digital inputs not being restricted by the v dd + 0.3 v limit is that the power supply sequencing issues are avoided. if any of these inputs are applied before v dd , there is no risk of latch-up as there is on the analog inputs if a signal greater than 0.3 v is applied prior to v dd . v drive input the ad7934-6 also has a v drive feature. v drive controls the voltage at which the parallel interface operates. v drive allows the adc to easily interface to 3 v and 5 v processors. for example, if the ad7934-6 is operated with a v dd of 5 v, and the v drive pin is powered from a 3 v supply, the ad7934-6 has better dynamic performance with a v dd of 5 v while still being able to interface to 3 v processors. care should be taken to ensure v drive does not exceed v dd by more than 0.3 v (see the absolute maximum ratings section).
ad7934-6 rev. b | page 21 of 28 parallel interface the ad7934-6 has a flexible, high speed, parallel interface. this interface is 12 bits wide and is capable of operating in either word (w/ b tied high) or byte (w/ b tied low) mode. the convst signal is used to initiate conversions and, when operating in autoshutdown or autostandby mode, it is used to initiate power-up. a falling edge on the convst signal is used to initiate conver- sions, and it also puts the adc track-and-hold into track. once the convst signal goes low, the busy signal goes high for the duration of the conversion. between conversions, convst must be brought high for a minimum time of t 1 . this must occur after the 14 th falling edge of clkin; otherwise, the conversion is aborted and the track-and-hold goes back into track. at the end of the conversion, busy goes low and can be used to activate an interrupt service routine. the cs and rd lines are then activated in parallel to read the 12 bits of conversion data. when power supplies are first applied to the device, a rising edge on convst is necessary to put the track-and-hold into track. the acquisition time of 125 ns minimum must be allowed before convst is brought low to initiate a conversion. the adc then goes into hold on the falling edge of convst , and back into track on the 13 th rising edge of clkin (see figure 34 ). when operating the device in autoshutdown or autostandby mode, where the adc powers down at the end of each conversion, a rising edge on the convst signal is used to power up the device. t 2 t 3 t 20 t 14 t 11 t 9 t 13 t 12 t 10 t convert t acquisition t quiet t 1 12 345 121314 b a data data old data db0 to db11 db0 to db11 rd cs internal track/hold busy clkin convst three-state three-state 04752-004 with cs and rd tied low figure 34. ad7934-6 parallel interfaceconversion and read cycle timing in word mode (w/ b = 1)
ad7934-6 rev. b | page 22 of 28 reading data from the ad7934-6 with the w/ b pin tied logic high, the ad7934-6 interface operates in word mode. in this case, a single read operation from the device accesses the conversion data-word on pin db0 to pin db11. the db8/hben pin assumes its db8 function. with the w/ b pin tied to logic low, the ad7934-6 interface operates in byte mode. in this case, the db8/hben pin assumes its hben function. conversion data from the ad7934-6 must be accessed in two read operations with eight bits of data provided on db0 to db7 for each of the read operations. the hben pin determines whether the read operation accesses the high byte or the low byte of the 12-bit word. for a low byte read, db0 to db7 provide the eight lsbs of the 12-bit word. for a high byte read, db0 to db3 provide the four msbs of the 12-bit word. db4 and db5 of the high byte provide the channel id. db6 and db7 are always 0. figure 34 shows the read cycle timing diagram for a 12-bit transfer. when operated in word mode, the hben input does not exist and only the first read operation is required to access data from the device. when operated in byte mode, the two read cycles shown in figure 35 are required to access the full data-word from the device. the cs and rd signals are gated internally and the level is triggered active low. in either word mode or byte mode, cs and rd can be tied together as the timing specification t 10 and t 11 are 0 ns minimum. this means the bus is constantly driven by the ad7934-6. the data is placed onto the data bus a time, t 13 , after both cs and rd go low. the rd rising edge can be used to latch data out of the device. after a time, t 14 , the data lines become three-stated. alternatively, cs and rd can be tied permanently low, and the conversion data is valid and placed onto the data bus a time, t 9 , before the falling edge of busy. note that if rd is pulsed during the conversion time, this causes a degradation in linearity performance of approximately 0.25 lsb. reading during conversion by way of tying cs and rd low does not cause any degradation. t 11 t 10 t 13 t 15 t 15 t 16 t 16 t 14 t 12 t 17 low byte high byte db0 to db7 hben/db8 rd cs 04752-005 figure 35. ad7934-6 parallel interfaceread cycle timing for byte mode operation (w/ b = 0)
ad7934-6 rev. b | page 23 of 28 writing data to the ad7934-6 with w/ b tied logic high, a single write operation transfers the full data-word on db0 to db11 to the control register on the ad7934-6. the db8/hben pin assumes its db8 function. data written to the ad7934-6 should be provided on the db0 to db11 inputs, with db0 being the lsb of the data-word. with w/ b tied logic low, the ad7934-6 requires two write operations to transfer a full 12-bit word. db8/hben assumes its hben function. data written to the ad7934-6 should be provided on the db0 to db7 inputs. hben determines whether the byte written is high byte or low byte data. the low byte of the data- word has db0 being the lsb of the full data-word. for the high byte write, hben should be high, and the data on the db0 input should be data bit 8 of the 12-bit word. figure 36 shows the write cycle timing diagram of the ad7934-6. when operating in word mode, the hben input does not exist, and only one write operation is required to write the word of data to the device. data should be provided on db0 to db11. when operating in byte mode, the two write cycles shown in figure 37 are required to write the full data-word to the ad7934-6. in figure 37 , the first write transfers the lower eight bits of the data-word from db0 to db7, and the second write transfers the upper four bits of the data-word. when writing to the ad7934-6, the top four bits in the high byte must be 0s. the data is latched into the device on the rising edge of wr . the data needs to be set up a time, t 7 , before the wr rising edge and held for a time, t 8 , after the wr rising edge. the cs and wr signals are gated internally. cs and wr can be tied together as the timing specification for t 4 , and t 5 is 0 ns minimum (assuming cs and rd have not already been tied together). t 8 t 5 t 7 t 6 t 4 data db0 to db11 wr cs 04752-002 figure 36. ad7934-6 parallel interfacewrite cycle timing for word mode operation (w/ b = 1) t 5 t 4 t 7 t 18 t 18 t 19 t 19 t 8 t 6 t 17 low byte high byte db0 to db7 hben/db8 wr cs 04752-003 figure 37. ad7934-6 parallel interfacewrite cycle timing for byte mode operation (w/ b = 0)
ad7934-6 rev. b | page 24 of 28 power modes of operation the ad7934-6 has four different power modes of operation. these modes are designed to provide flexible power manage- ment options. different options can be chosen to optimize the power dissipation/throughput rate ratio for differing applications. the mode of operation is selected by the power management bits, pm1 and pm0, in the control register (see table 8 ). when power is first applied to the ad7934-6, an on-chip, power-on reset circuit ensures that the default power-up condition is normal mode. note that, after power-on, the track-and-hold is in hold mode, and the first rising edge of convst , places the track-and-hold into track mode. normal mode (pm1 = pm0 = 0) this mode is intended for the fastest throughput rate perform- ance because the user does not have to allow for power-up times associated with the ad7934-6. it remains fully powered up at all times. at power-on reset, this mode is the default setting in the control register. autoshutdown mode (pm1 = 0; pm0 = 1) in this mode of operation, the ad7934-6 automatically enters full shutdown at the end of each conversion, shown at point a in figure 34 and figure 38 . in shutdown mode, all internal circuitry on the device is powered down. the part retains information in the control register during shutdown. the track- and-hold also goes into hold at this point, and remains in hold as long as the device is in shutdown. the ad7934-6 remains in shutdown mode until the next rising edge of convst (see point b in figure 34 and figure 38 ). to keep the device in shutdown for as long as possible, convst should idle low between conversions, as shown in figure 38 . on this rising edge, the part begins to power up and the track-and-hold returns to track mode. the power-up time required is 10 ms minimum regardless of whether the user is operating with the internal or external reference. the user should ensure that the power-up time has elapsed before initiating a conversion. autostandby mode (p m1 = 1; pm0 = 0) in this mode, the ad7934-6 automatically enters standby mode at the end of each conversion, shown as point a in figure 34 . when this mode is entered, all circuitry on the ad7934-6 is powered down except for the reference and reference buffer. the track-and-hold also goes into hold at this point and remains in hold as long as the device is in standby. the part remains in standby until the next rising edge of convst powers up the device. the power-up time required depends on whether the internal or external reference is used. with an external reference, the power-up time required is a minimum of 600 ns. when using the internal reference, the power-up time required is a minimum of 7 s. the user should ensure this power-up time has elapsed before initiating another conversion as shown in figure 38 . this rising edge of convst also places the track-and-hold back into track mode. full shutdown mode (pm1 = 1; pm0 = 1) when this mode is entered, all circuitry on the ad7934-6 is powered down upon completion of the write operation, that is, on the rising edge of wr . the track-and-hold enters hold mode at this point. the part retains the information in the control register while the part is in shutdown. the ad7934-6 remains in full shutdown mode, with the track-and-hold in hold mode, until the power management bits (pm1 and pm0) in the control register are changed. if a write to the control register occurs while the part is in full shutdown mode, and the power management bits are changed to pm0 = pm1 = 0 (normal mode), the part begins to power up on the wr rising edge, and the track-and-hold returns to track. to ensure the part is fully powered up before a conversion is initiated, the power-up time of 10 ms minimum should be allowed before the convst falling edge; otherwise, invalid data is read. note that all power-up times quoted apply with a 470 nf capacitor on the v refin pin. t power-up 1 1 14 14 busy clkin convst 04752-048 a b figure 38. autoshutdo wn/autostandby modes
ad7934-6 rev. b | page 25 of 28 power vs. throughput rate a considerable advantage of powering the adc down after a conversion is that the parts power consumption is significantly reduced at lower throughput rates. when using the different power modes, the ad7934-6 is only powered up for the duration of the conversion. therefore, the average power consumption per cycle is significantly reduced. figure 39 shows a plot of the power vs. the throughput rate when operating in autostandby mode for both v dd = 5 v and 3 v. for example, if the device runs at a throughput rate of 10 ksps, the overall cycle time is 100 s. if the maximum clkin frequency of 10 mhz is used, the conversion time accounts for only 1.315 s of the overall cycle time while the ad7938-6 stays in standby mode for the remainder of the cycle. if an external reference is used, the power-up time reduces to 600 ns; therefore, the ad7934-6 remains in standby for a greater time in every cycle. additionally, the current consumption when converting should be lower than the specified maximum of 1.5 ma or 1.2 ma with v dd = 5 v or 3 v, respectively. figure 40 shows a plot of the power vs. the throughput rate when operating in normal mode for both v dd = 5 v and 3 v. again, when using an external reference, the current consumption when converting is lower than the specified maximum. in both plots, figure 39 and figure 40 apply when using the internal reference. throughput (ksps) power (mw) 2.0 0.2 0.4 0.6 0.8 1.2 1.6 1.0 1.4 1.8 0 020406080 1 100 04752-029 20 t a = 25c v dd =5v v dd =3v figure 39. power vs. throughput in autostandby mode using internal reference throughput (ksps) power (mw) 7 4 5 6 0 3 2 1 0 100 200 300 400 500 700 600 04752-030 t a = 25c v dd =5v v dd =3v figure 40. power vs. throughput in normal mode using internal reference microprocessor interfacing ad7934-6 to adsp-21xx interface figure 41 shows the ad7934-6 interfaced to the adsp-21xx series of dsps as a memory-mapped device. a single wait state could be necessary to interface the ad7934-6 to the adsp-21xx, depending on the clock speed of the dsp. the wait state can be programmed via the data memory wait state control register of the adsp-21xx (see the adsp-21xx family users manual for details). the following instruction reads from the ad7934-6: mr = dm ( adc ) where: adc is the address of the ad7934-6. ad7934-6* adsp-21xx* wr rd db0 to db11 d0 to d23 a0 to a15 dms irq2 busy cs convst dsp / user system wr rd *additional pins omitted for clarity. address bus data bus address decoder 04752-044 figure 41. interfacing to the adsp-21xx
ad7934-6 rev. b | page 26 of 28 ad7934-6 to adsp-21065l interface figure 42 shows a typical interface between the ad7934-6 and the adsp-21065l sharc processor. this interface is an example of one of three dma handshake modes. the ms x control line is actually three memory select lines. internal addr 25 to 24 are decoded into ms 3 to 0 . these lines are then asserted as chip selects. the dmar 1 (dma request 1) is used in this setup as the interrupt to signal the end of the conversion. the rest of the interface is a standard handshaking operation. ad7934-6* adsp-21065l* wr db0 to db11 d0 to d31 addr 0 to addr 23 ms x dmar 1 busy cs convst dsp / user system wr rd rd *additional pins omitted for clarity. address bus address bus data bus address latch address decoder 04752-045 figure 42. interfacing to the adsp-21065l ad7934-6 to tms32020, tms320c25, and tms320c5x interface parallel interfaces between the ad7934-6 and the tms32020, tms320c25, and tms320c5x family of dsps are shown in figure 43 . the memory-mapped address chosen for the ad7934-6 should be chosen to fall in the i/o memory space of the dsps. the parallel interface on the ad7934-6 is fast enough to interface to the tms32020 with no extra wait states. if high speed glue logic devices, such as the 74as, are used to drive the rd and the wr lines when interfacing to the tms320c25, no wait states are necessary. however, if slower logic is used, data accesses could be slowed sufficiently when reading from, and writing to, the part to require the insertion of one wait state. extra wait states are necessary when using the tms320c5x at their fastest clock speeds (see the tms320c5x users guide for details). data is read from the adc using the following instruction: in d , adc where: d is the data memory address. adc is the ad7934-6 address. ad7934-6* tms32020/ tms320c25/ tms320c50* wr rd db11 to db0 dmd0 to dmd15 a0 to a15 is ready int x busy cs en convst dsp / user system tms320c25 only r/w strb *additional pins omitted for clarity. address bus data bus address decoder 04752-046 msc figure 43. interfacing to the tms32020/tms320c25/tms320c5x ad7934-6 to 80c186 interface figure 44 shows the ad7934-6 interfaced to the 80c186 microprocessor. the 80c186 dma controller provides two independent high speed dma channels where data transfer can occur between memory and i/o spaces. each data transfer consumes two bus cycles, one cycle to fetch data and the other to store data. after the ad7934-6 has finished a conversion, the busy line generates a dma request to channel 1 (drq1). because of the interrupt, the processor performs a dma read operation that also resets the interrupt latch. sufficient priority must be assigned to the dma channel to ensure that the dma request is serviced before the completion of the next conversion. ad7934-6* 80c186* wr db0 to db11 ad0 to ad15 a16 to a19 ale drq1 busy cs qr s convst microprocessor/ user system wr rd rd * additional pins omitted for clarity. address/data bus address bus data bus address latch address decoder 04752-047 figure 44. interfacing to the 80c186
ad7934-6 rev. b | page 27 of 28 application hints grounding and layout the printed circuit board that houses the ad7934-6 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. generally, a minimum etch technique is best for ground planes since it gives the best shielding. digital and analog ground planes should be joined in only one place, and the connection should be a star ground point established as close to the ground pins on the ad7934-6 as possible. avoid running digital lines under the device as this couples noise onto the die. the analog ground plane should be allowed to run under the ad7934-6 to avoid noise coupling. the power supply lines to the ad7934-6 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with 10 f tantalum capacitors in parallel with 0.1 f capacitors to gnd. to achieve the best performance from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. the 0.1 f capacitors should have low effective series resistance (esr) and effective series inductance (esi), such as the common ceramic types or surface-mount types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. evaluating the ad7934-6 performance the recommended layout for the ad7934-6 is outlined in the evaluation board documentation. the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the pc via the evaluation board controller. the evaluation board controller can be used in conjunction with the ad7934-6 evaluation board, as well as with many other analog devices evaluation boards ending in the cb designator, to demonstrate and evaluate the ac and dc performance of the ad7934-6. the software allows the user to perform ac (fast fourier transform) and dc (histogram of codes) tests on the ad7934-6. the software and documentation are on the cd that ships with the evaluation board.
ad7934-6 rev. b | page 28 of 28 outline dimensions compliant to jedec standards mo-153-ae 28 15 14 1 8 0 seating plane c oplanarit y 0.10 1.20 max 6.40 bsc 0.65 bsc pin 1 0.30 0.19 0.20 0.09 4.50 4.40 4.30 0.75 0.60 0.45 9.80 9.70 9.60 0.15 0.05 figure 45. 28-lead thin shrink small outline package [tssop] (ru-28) dimensions shown in millimeters ordering guide model temperature range linearity error (lsb) 1 package description package option ad7934bru-6 ?40c to +85c 1 28-lead tssop ru-28 ad7934bru-6reel7 ?40c to +85c 1 28-lead tssop ru-28 ad7934bruz-6 2 ?40c to +85c 1 28-lead tssop ru-28 ad7934bruz-6reel7 2 ?40c to +85c 1 28-lead tssop ru-28 eval-ad7934-6cb 3 evaluation board EVAL-CONTROL-BRD2 4 controller board 1 linearity error here refers to integral linearity error. 2 z = pb-free part. 3 this can be used as a standalone evaluation board or in conjunction with the evaluation board controller for evaluation/demons tration purposes. 4 the evaluation board controller is a complete unit that allows a pc to control and communicate with all analog devices evaluat ion boards ending in the letters cb. the following needs to be ordered to obtain a complete evaluation kit: the adc evaluation board (for example, eval-ad7934cb), t he EVAL-CONTROL-BRD2, and a 12 v ac transformer. see the relevant evaluation board data sheet for more details. ?2005C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04752-0- 2 /07(b)

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